The present invention relates to the field of echo cancellers, and in particular to an echo canceller that includes an adaptive filter that employs a dynamically adjustable step size.
As known, bothersome echoes occur in communication systems, such as telephone systems, that operate over long distances or in systems that employ long processing delays, such as digital cellular systems. The echoes are the result of electric leakage in the four-to-two/two-to-four wire hybrid circuit, due to an impedance mismatch in the hybrid circuit between the local loop wire and the balance network. To reduce the echoes, communication systems typically include one or more echo cancellers.
FIG. 1 is a block diagram illustration of a communication system 10 that connects at least two subscribers 12, 14. The first subscriber 12 is typically connected to the communication system 10 via a two-wire line 16 and a hybrid circuit 18. The hybrid circuit 18 connects the two-wire line 16 to the four-wire lines 20, 22. The first four-wire line 20 provides a signal to the second subscriber via a second hybrid circuit 24 and a two-wire line 26. Similarly, signals from the second subscriber 14 are routed to the first subscriber 12 over the two-wire line 26, the second hybrid circuit 24 and the four-wire line 20, 22. In one application, the hybrid circuits may be located in the telephone company central offices. To reduce the echo signals coupled by the hybrid circuit due to impedance mismatches, echo cancellers 30, 32 are included to attenuate the undesirable echoes.
Echo cancellers typically include an adaptive filter that generates an estimate of the echo and subtracts the estimate from the return signal. Like any adaptive discrete time filter, the tap weights of the filter are adjusted based upon the difference between the estimate of the echo signal and the return signal. The adaptive filter employs an adaptive control algorithm to adjust the tap weights in order to drive the value of the difference signal to zero or a minimum value.
A problem with prior art echo cancellers is the relatively long time it takes for the adaptive control algorithm to adapt the filter tap weights in order to drive the error signal value to zero. This is often referred to as speed of convergence. A widely used technique for adapting the tap weights is referred to as the least-mean-square (LMS) algorithm. Advantageously, the LMS algorithm is relatively easy to implement since it does not require measurements of the pertinent correlation functions, nor does it require matrix inversions. In order to decrease the amount of time it takes to drive the difference signal to zero, the adaptive control algorithm may adjust the step size μ used in the LMS algorithm to a larger value. Although using a relatively large fixed step size μ facilitates a rapid convergence, the large step size results in a relatively large residual error following convergence. As a trade-off between rapid convergence and a small residual error, some systems have employed a relatively large step size initially and then switch to a smaller predetermined step size as a function of sample count (i.e., time). This approach takes advantage of the improved speed of convergence associated with the initial large step size value, and the relatively small residual error associated with the smaller step size value.
Another problem with prior art echo cancellers has been the relatively large computational burden associated with the echo cancellers. In a digital signal processor embodiment (DSP), the echo canceller requires a relatively large percentage of the DSP's available processing power (e.g., MIPS). Similarly, in an application specific integrated circuit (ASIC) embodiment the relatively large computational burden leads to the use of a large number of gates to implement the echo canceller.
U.S. Pat. No. 6,223,194 entitled “Adaptive Filter, Step Size Control Method Thereof, and Record Medium Therefor” discloses various embodiments for adjusting the step size. However, a problem with the techniques and embodiments set forth in U.S. Pat. No. 6,223,194 is that they require a divide operation in order to compute the step size. Divide operations are undesirable in both DSP embodiments and ASIC embodiments of echo cancellers. Other embodiments disclosed in U.S. Pat. No. 6,223,194 are also computationally inefficient due to their need to compute square roots and vector norms.
Therefore, there is a need for an improved technique for dynamically adjusting the step size μ in an echo canceller having an adaptive filter that employs a stochastic quadratic descent algorithm such as LMS.